1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of operation modes, each operated with its inherent operation speed. More particularly, it relates to a semiconductor memory device and non-volatile semiconductor memory device that conduct successive operations by generating addresses subsequently among different operation modes.
2. Description of Related Art
Recent years, there have been popularized semiconductor memory devices that have a plurality of operation modes, each operated with its inherent operation speed. To be specific, the operation modes are classified into: readout operation; write operation; and erase operation. The readout operation is conducted at high-speed whereas the write and erase operations take much longer than the readout operation because the latter two operations accompany materialistic operations such as charge-injection to a floating gate and charge-emission from there. As semiconductor memory device having a plurality of operation modes among which operation speeds differ significantly, non-volatile semiconductor memory devices such as flash memory have been widely used for portable appliances.
Flash memory has conventionally been used as a device to record comparatively small volume of information such as memory of operational conditions for portable appliance or memory of concise information such as personal notes for user. Therefore, readout and write operations are united to be single operation such that input and output of data is made for single memory cell corresponding to an address given from the external. The operational specification is designed to be compatible with asynchronous static RAM (referred to as SRAM herein after). Erase operation can apply to pluralities of memory cell during one operational cycle. However, similar to readout and write operations, each cycle of erase operation goes in asynchronous with other operation modes.
On the other hand, portable appliances these days are required to handle even larger volume of information at high-speed, for example, transmission and receipt of image information by a cellular phone. Therefore, for system of portable appliances, there have been studied specifications having affinity with synchronous dynamic random access memory (SDRAM hereinafter) that operates in synchronous with system clock. Along with the trend, a flash memory is also required to have an operation mode such as burst operation that is compatible with system for SDRAM and changes addresses incessantly. In a word, there has been required a synchronous flash memory.
In design of synchronous flash memory, it is conceived to use structure of SDRAM. That is, provided that an address taken from the external is regarded as a start address, it is conceived of a synchronous flash memory provided with an address counter for counting up an address value in synchronous with a system clock, a control counter for counting burst values and the like.
However, speed of readout operation for a flash memory is determined by electric transmission delay due to its circuit structure. On the other hand, speed of write operation takes significantly longer than that of electric operation speed. This is because data is written in accordance with physical phenomenon called avalanche-breakdown phenomenon caused by high-field application of charges, whereby charges are injected to a floating gate of memory cells to write data. Similar to write operation, speed of erase operation takes significantly longer than that of electric operation because data is erased in accordance with physical phenomenon called tunneling caused by high-field application of charges, whereby charges are emitted from the floating gate of memory cells to erase data. Since the above-described operations are conducted with different mechanism, speeds of the respective operations differ. For example, as for flash memory MBM29LV800TA/BA-70, product of FUJITSU LIMITED, readout operation takes 70 n sec. at maximum as address access time (tACC) whereas program duration (tWHWH1) as write operation time takes 8 xcexcsec. as standard value and sector-erase duration (tWHWH2) as erase operation time takes 1 sec. as standard value. Speeds of the respective operation modes thus differ significantly. To make comparison with an SDRAM that has only two operation modes, namely, readout and write modes, and speed levels of the two operation modes are generally same, which derives from electric transmission delay due its circuit structure, the flash memory has at least three operation modes and each of the operation modes works along different mechanism. Therefore, it is not feasible that each operation mode of a flash memory makes use of SDRAM circuit structure to realize optimal operation for respective operation modes. This is a problem conventional flash memory faces.
The problem such as the above will be described by referring to FIG. 6 that shows a timing chart regarding burst operation of a flash memory. In FIG. 6, operation condition is set to: burst length=2; write (program) latency=0; and readout latency=2. In synchronous with an external clock signal CLK, a write (program) command PGM is received for Bank A designated by a bank address (Bank Add). PA0, a reference address of an external address (External Add.) is received for the write (program) command PGM. Further on, 2-bit write (program) data D0 and D1 are inputted in synchronous with each cycle of the external clock signal CLK. During a cycle of the clock signal CLK where the write (program) command PGM is inputted, the external address PA0 is set in an address counter as an internal address (Internal Add.). Based on the internal address (Internal Add.), writing (programming) of data D0 in the address PA0 is started. Since write (program) operation is conducted in accordance with the as-mentioned physical phenomenon, including verify operation for verifying completion of correct data-write, it takes long to complete the write (program) operation. After the write (program) operation completes, the address counter makes an increment in the number of address from PA0 to PA1 so as to start writing (programming) data D1 for a new address PA1.
Let us take a case wherein a readout command READ for a Bank B is received in synchronous with an external clock signal CLK to start burst readout operation at time t0 when write (program) operation is being conducted. The bank B is designated by the bank address (Bank Add.) and the readout command READ is a command whose reference address is an external address (External Add.) RA0. Since speed of the readout operation is determined by electric transmission delay due to its circuit structure, data can be outputted in the same manner as operation of SDRAM. However, a cycle of write (program) operation is longer than that of readout operation and cycle lengths of these two operation cycles are great difference, write (program) operation and readout operation cannot share and use one address counter subsequently like bust operation in a conventional SDRAM. That is, since write (program) operation to an address PA1 has not finished at time t0, in case burst-readout operation is inserted, write (program) operation must be suspended and resumed after completion of readout operation so as to avoid a scramble for an address of the address counter. Specifically, in order to stop write (program) operation temporarily, there are needed operations to: stop write (program) operation; drive out a write (program) address from the address counter or record the address driven out in there; drive out a burst value from a control counter or record the valve driven out in there; take a reference address into the address counter for burst-readout operation; set a burst value in the control counter during burst-readout operation and the like. Numbers of operations just for stopping write (program) operation temporarily make the operation system complicated, which is problematic. Similarly, in order to resume write (program) operation, there are needed complicated and numbers of controls to: detect completion of readout operation; take a write (program) address that has been driven out or recorded there into the address counter; take a burst value address that has been driven out or recorded there into the control counter. Thus, resume operation is complicated and problematic, either.
In addition, since a cycle of readout operation and that of write (program) operation differ significantly, it is necessary to switch count cycles of the address counter depending on respective operations. Along with that, switching control of a count-up timing generator circuit or the like must be conducted simultaneously. This makes a manner of control complicated.
Since suspension of write (program) operation accompanies serial complicated controls and switching control of count cycles for the address counter, resumption of write (program) operation after switching needs a predetermined length of delay time ({circumflex over (1)} in FIG. 6). Accordingly, in order to surely conduct readout operation at the reference address RA0 after interruption of write (program) operation, a sum of a readout operation time and a delay time until setting the reference address RA0 must be taken as an operation cycle. Since resumption of write operation also accompanies serial complicated controls and switching control of count cycles for the address counter, resumption of write (program) operation after switched needs a predetermined length of delay time ({circumflex over (2)} in FIG. 6). Accordingly, a time including a predetermined length of delay time is needed as a resume operation cycle. Due to the inclusion of the delay time, the entire operations for read and write slow down to keep pace with interruption and resumption operation cycles. This is an obstacle to high-speed responsibility for a flash memory.
The above description mentions a case that a readout operation is inserted during a write (program) operation, as an example. However, any combinations of read, write (program), and erase operations need complicated controls because lengths of respective operation cycles differ significantly and this is an obstacle to high-speed responsibility in the event.
The present invention is intended to solve the foregoing prior art deficiency. Its prime object, in a semiconductor memory device having a plurality of operation modes operated with their respective operation, is to enhance performance of successive operations conducted by generating addresses subsequently for different operation modes. More particularly, it is intended to provide a synchronous non-volatile semiconductor memory device having operational performance as high as SDRAM.
In order to achieve the above objective, the semiconductor memory device based on one aspect of this invention, which has a first operation mode operable with a first cycle and a second operation mode operable with a second cycle that is longer than the first cycle, comprises: a first address counter that generates addresses with the first operation mode; and a second address counter that generates addresses with the second operation mode.
In the inventive semiconductor memory device, the first address counter generates addresses with the first operation mode by the first cycle whereas the second address counter generates addresses with the second operation mode by the second cycle. Since a second cycle is longer than a first cycle, the second counter takes longer time of a cycle to generate address than the first counter does.
Thereby, in the semiconductor memory device, there can be separately arranged two address counters that have respective operation cycles, namely, the first address counter and the second address counter, to meet two different operation modes, namely, the first operation mode and the second operation mode. Therefore, there occurs no operational conflicts even if addresses directed to the two different operations modes are outputted in the internal simultaneously. Accordingly, even if operation modes are changed, appropriate numbered address can be outputted to address buses at any time without initializing the address counter. Thus there are avoided serial complicated controls such as replacements of address values at the address counters, suspension of operation modes due to the replacements, resumption of the suspended operation and the like. Since there occurs no delay time due to the complicated control operations, high-speed data transfer rate can be realized.
Furthermore, a semiconductor memory device based on another aspect of the invention, that has a first operation mode operable with a first cycle and a second operation mode operable with a second cycle that is longer than the first cycle, comprises: a first address counter that generates addresses in serial order subsequent to a first reference address by first cycle generated in synchronous with a clock signal supplied from an external section with the first operation mode; and a second address counter that generates addresses in serial order subsequent to a second reference address by second cycle generated in asynchronous with a clock signal supplied from an external section with the second operation mode.
In the inventive semiconductor memory device, the first address counter that generates addresses in serial order subsequent to a first reference address by first cycle generated in synchronous with a clock signal supplied from an external section with the first operation mode, and the second address counter that generates addresses in serial order subsequent to a second reference address by second cycle generated in asynchronous with a clock signal supplied from an external section with the second operation mode.
Thereby, there occurs no operational conflicts even if addresses are generated simultaneously from operation modes operable in synchronous with an external clock signal and from other operation mode operable in asynchronous with an external clock signal. Therefore, addresses can be outputted to internal address buses at any time with timing appropriate to respective operation modes without initializing each address counter. Thus there are avoided serial complicated controls such as replacements of address values at the address counters, suspension of operation modes due to the replacements, resumption of the suspended operation and the like. Since there occurs no delay time due to the complicated control operations, high-speed data transfer rate can be realized.
A non-volatile semiconductor memory device based on one aspect of the present invention that has readout mode operable with first cycle and write mode or erase mode operable with second cycle that is longer than the first cycle comprises: a first address counter that generates addresses in serial order subsequent to a first reference address by the first cycle generated in synchronous with a clock signal supplied from an external section with the readout mode; and a second address counter that generates addresses in serial order subsequent toa second reference address by the second cycle generated in synchronous with a clock signal supplied from an external section with either the write mode or the erase mode.
In the inventive non-volatile semiconductor memory device, in the readout mode, the first address counter generates addresses in serial order subsequent to the first reference address by the first cycle, whereas in the write mode or the erase mode, the second address counter generates addresses in serial order subsequent to the second reference address by the second cycle. In this case, both the first cycle and the second cycle are generated in synchronous with clock signals supplied from an external section keeping relationship that a second cycle is longer than a first cycle.
Thus there are used two address counters operable with two different operation cycles, one for readout mode operable in first cycle and the other for write or erase mode operable in second cycle, in the non-volatile semiconductor memory device. Accordingly, there occurs no operational conflicts even if addresses are generated simultaneously from respective operation modes. Even if operation modes are changed, addresses can be outputted to internal address buses at any time without initializing each address counter.
Furthermore, since the first address counter and the second address counter can generate addresses in serial order subsequent to the first reference address and the second reference address, respectively, each of the address counters can dependently generate appropriate addresses in serial order subsequent to respective reference addresses. Therefore, addresses can be outputted to internal address buses at any time based on appropriate reference addresses without initializing each address counter among readout mode, write mode, and erase mode.
Still further, two operation cycles different in length wherein second cycle is longer than first cycle can be synchronized with clock signals supplied from an external section.
Thus there are avoided serial complicated controls such as replacements of address values at the address counters, suspension of operation modes due to the replacements, resumption of the suspended operation and the like. Since there occurs no delay time due to the complicated control operations, high-speed data transfer rate can be realized.
A non-volatile semiconductor memory device based on another aspect of the present invention that has readout mode operable with first cycle and write mode or erase mode operable with second cycle that is longer than the first cycle comprises: a first address counter that generates addresses in serial order subsequent to a first reference address by the first cycle generated in synchronous with a clock signal supplied from an external section with the readout mode; and a second address counter that generates addresses in serial order subsequent to a second reference address by the second cycle generated in asynchronous with a clock signal supplied from an external section with either the write mode or the erase mode.
In the inventive non-volatile semiconductor memory device, in the readout mode, the first address counter generates addresses in serial order subsequent to the first reference address by the first cycle, whereas in the write mode or the erase mode, the second address counter generates addresses in serial order subsequent to the second reference address by the second cycle. In this case, the first cycle is generated in synchronous with a clock signal outputted from an external section whereas the second cycle is generated in asynchronous with a clock signal.
Thereby, even if it is between readout mode operable in synchronous with external clock signals and write or erase mode operable in asynchronous with external clock signals, there occurs no operational conflicts even if addresses are generated simultaneously from respective operation modes there. Therefore, addresses can be outputted to internal address buses at any time with timing appropriate to respective operation modes without initializing each address counter. Thus there are avoided serial complicated controls such as replacements of address values at the address counters, suspension of operation modes due to the replacements, resumption of the suspended operation and the like. Since there occurs no delay time due to the complicated control operations, high-speed data transfer rate can be realized.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.